As microprocessors become faster and smaller, integrated circuitry (IC) becomes more complex and components become more densely packed. Interconnect lines are needed to provide electrical connections to different portions of the device. The current patterning technique for forming interconnect lines includes the formation of trenches that have a uniform depth, as shown in FIG. 1. Conductive material is then disposed into the trenches to form interconnect lines 120. However, as the pitch of the interconnect lines decrease, increases in the line-to-line capacitances between neighboring interconnect lines becomes a limiting factor. Prior attempts to decrease the line-to-line capacitance rely on low-k dielectric materials and techniques such as using air pockets. However, these approaches are limited by material properties and generally result in poor structural integrity.
In addition to the increase in the line-to-line capacitance, shrinking the pitch of the interconnect lines increases the demands on masking and etching processes required for the formation of connections to the interconnect lines from subsequent layers. In FIG. 1, a contact mask 160 is disposed over the etch stop layer 105. In order to make a contact to a single interconnect line 120, the contact mask 160 must be patterned to have a mask opening M that is aligned over a single interconnect line 120. If the mask opening M is misaligned and extends over a neighboring interconnect line 120, as shown in FIG. 1, then the etching process would provide contacts to both interconnect lines, thereby preventing the formation of an isolated connection. Accordingly, reducing the pitch of the interconnect lines requires aligning and patterning contact masks with increased precision that may not be obtainable with conventional lithography processes.